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EEBookshelf: High Speed PCB Layout

PCB layout is tough.  Laying out a PCB isn’t in itself too hard once you learn how the tools work, but high-speed (10MHz+) introduces a virtual mine field of potential issues that you may not be aware of until it’s too late.  While experience is the best teacher, Analog Devices has a great application note explaining some of the key pitfalls to avoid when dealing with high speed designs (which is basically anything today): A Practical Guide to High-Speed Printed-Circuit-Board Layout.  Some of it is a bit heady, but not more than it needs to be, and it really does lay out a lot of key information that you may not have been aware of.  Want to improve your PCB design skills?  Print this out, and keep reading through it until it starts to make sense.  There’s years of bench time worth of information in there.


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4 Comments

  1. This actually gives me an idea. I am currently testing a new amplifier and the phase margin actually INCREASES with a heavier capacitive load. This flies in the face of theory. I have already included the trace inductance and lead inductance of the capacitor in SPICE.
    I have not included parasitic affects around the summing node, so maybe that may yield some light on the issue.
    Usually though, my rule of thumb for high speed design is 50MHz+.

  2. Good stuff

  3. Good Book! I’ve been reading through this recently as I design my first RF circuit, and it’s been an amazing help.

  4. * Good article, rather.

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