EE Bookshelf: PCB Layout for BGA Packages (AN10778)
If you’ve ever been curious about how to properly define BGA footprints or what patterns to use for BGA ‘fan-out’ (breaking the signals out from underneath the chip), AN10778 from NXP provides a lot of helpful information on some common BGA packages. 1.0mm and 0.8mm pitch BGA actually aren’t that bad to work with and you don’t need to pay for super-exotic tolerances from your board house, plus bridges underneath are reasonably rare if you have a good paste layer and footprint. It does get a lot more challenging and expensive from 0.65mm and lower, but NXP provides some good suggestions and clear numbers on how to handle both situations.
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Kevin, you seem endlessly capable of finding interesting things to read and learn. Thanks for sharing!
I’ve got a small stack of FPGAs in a BGA package, and have been vaguely considering building some PCBs for them for some time. This is a push toward actually doing that.
Jack: Thanks for the kind words, but almost all of this is just from floundering around in the dark myself at some point in the past. 🙂
FPGAs tend to be a lot tighter pitch, but Lattice also has a decent technical note on this: TN1074. You’re job is a lot easier if there are only four or so rows of balls and some space in the middle, but if you have a solid 16×16 array or something like that it can get tough to route at 0.65mm or 0.5mm, and you’ll need a lot more layers on the PCB.
I don’t mind working with 1.0mm and 0.8mm BGA since the boards aren’t terribly expensive and I can assemble them by hand, but 0.65mm really makes me hesistate, and I haven’t tried 0.5mm myself simply because the PCB cost in the volumes I need becomes the dominant factor. I had access to an XRay machine at my previous job for BGA inspection, but alas that’s not exactly something most people have the luxury of using post assembly to verify fine pitch BGA jobs.