CMOS 555 Timer: Structure Explained and Reverse Engineered
This is an amazing walkthrough from Ken Shirriff on the CMOS version of the 555 timer IC. Using a die shot from Zeptobars he examines transistors, gates, ‘how resistors are implemented in silicon,’ and much, much more in the low-power version of this venerable integrated circuit. If you’ve ever tinkered with the 555 – or, for that matter, any IC! – these are all probably points of interest that have further piqued your curiosity – and here they are, explained and reverse engineered!
The diagram below illustrates the internal operation of the 555 timer used as an oscillator. An external capacitor is repeatedly charged and discharged to produce the oscillation. Inside the 555 chip, three resistors form a divider generating reference voltages of 1/3 and 2/3 of the supply voltage. The external capacitor will charge and discharge between these limits, producing an oscillation, as shown on the left. In more detail, the capacitor will slowly charge (A) through the external resistors until its voltage hits the 2/3 reference. At that point (B), the threshold (upper) comparator switches the flip flop off turning the output off. This turns on the discharge transistor, slowly discharging the capacitor (C) through the resistor. When the voltage on the capacitor hits the 1/3 reference (D), the trigger (lower) comparator turns on, setting the flip flop and the output on, and the cycle repeats. The values of the resistors and capacitor control the timing, from microseconds to hours.
I especially dig this block-division of the die shot of the IC:
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