A Peek Inside Intel’s Hillsboro, Oregon Microprocessor Factory #ManufacturingMonday
Bloomberg Businessweek have a fairly lengthy article and an always-fun-to-see video with behind-the-scenes shots of Intel’s Hillsboro, Oregon microprocessor factory, a 17-million-cubic-foot facility where even the paper used is regulated to ensure it doesn’t “shed” microscopic matter that might land on a silicon wafer while it is being fabricated. Even for a split second it’s always intriguing to me to see where and when liquids are used in the manufacturing of anything, especially electronics – as the two are commonly not thought to be reliant on each other.
Before entering the cleanroom in D1D, as Intel calls its 17 million-cubic-foot microprocessor factory in Hillsboro, Oregon, it’s a good idea to carefully wash your hands and face. You should probably also empty your bladder. There are no bathrooms in the cleanroom. Makeup, perfume, and cosmetics are forbidden. Writing instruments are allowed, as long as they’re special sterile pens; paper, which sheds microscopic particles, is absolutely banned. If you want to write on something, you’ll have to use what is known in the industry as “high-performance documentation material,” a paperlike product that doesn’t release fibers.
After you put on a hairnet, your next stop is the gowning station, inside a pressurized room that sits between the outside world and the cleanroom itself. A hard breeze, sent by a cleaning system that takes up the equivalent of four and a half football fields, hits you as you walk in, removing stray matter—dust, lint, dog hairs, bacteria. You put on pre-gown gloves, then a white bodysuit with a hood and surgical-style mouth cover, followed by a second pair of gloves, a second pair of shoe covers, and safety glasses. None of these measures are for your safety; they protect the chips from you.
The air in the cleanroom is the purest you’ve ever breathed. It’s class 10 purity, meaning that for every cubic foot of air there can be no more than 10 particles larger than half a micron, which is about the size of a small bacteria. In an exceptionally clean hospital OR, there can be as many as 10,000 bacteria-size particles without creating any special risk of infection. In the outside world, there are about 3 million.
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The article referenced a “7.5-gigabyte file containing the full design” of the E5 processor. After some digging, I found that the E5 processor has ~7.2 Billion transistors(reference below). If both of those figures are correct, can someone explain how the location and orientation of each transistor, not to mention other relevant design information, can be described with barely more than 8 bits each? Perhaps previously designed libraries of sub-cores and other structures? I’m a noob, but am genuinely curious about this, am I missing something? Thanks!
Since the design is translated into a set of masks for each layer of the circuit, and masks are basically binary images (gigantic as they might be in this case), I would guess that there’s a lot of compression going on. And surely they didn’t design every single one of the 7 billion transistors, so there’s a lot of automation, which creates patterns that a compression algorithm can use to reduce the file size. Or one can just cut the middle man and put the design automation rules directly in the file, rather than the end result, and let the program regenerate them on the other end.