SKiDL is a module that allows you to compactly describe the interconnection of electronic circuits and components using Python. The resulting Python program performs electrical rules checking for common mistakes and outputs a netlist that serves as input to a PCB layout tool.
Has a powerful, flexible syntax (because it is Python).
Permits compact descriptions of electronic circuits (think about not tracing signals through a multi-page schematic).
Allows textual descriptions of electronic circuits (think about using diff and git for circuits).
Performs electrical rules checking (ERC) for common mistakes (e.g., unconnected device I/O pins).
Supports linear / hierarchical / mixed descriptions of electronic designs.
Fosters design reuse (think about using PyPi and Github to distribute electronic designs).
Makes possible the creation of smart circuit modules whose behavior / structure are changed parametrically (think about filters whose component values are automatically adjusted based on your desired cutoff frequency).
Can work with any ECAD tool (only two methods are needed: one for reading the part libraries and another for outputing the correct netlist format).
Takes advantage of all the benefits of the Python ecosystem (because it is Python).
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