Wicked decap and tour of the AD9361 by zeptobars:
When Analog Devices released their SDR transciever AD9361 in 2013 – it was a revolution in digital radio. SDR’s were there before, but only now you can have it all: 2 channels for TX and RX with onboard 12-bit DAC/ADCs with 56MHz of RF simultanious bandwidth, local oscillators, mixers and LNA – all working in the range from 70 (TX from 47) to 6000Mhz. Using AD9361 out of the box one could implement almost any useful digital radio, with the rare exceptions of UWB and 60GHz. You only need to add data source/sink (which is still often an FPGA), external filters and PA if your task requires it.
Finally I was able to take a look inside and peek at manufacturing cost of a microelectronic device with such an exceptional added value.
After decapsulation we see 4336×4730 µm 65nm die. On top metal you can notice PLL’s inductors and datecode – chip was somewhat ready 2 years before introduction:
On the right-bottom corner – main digital block, which should be the implementation of 128-tap FIR filter. In maximum magnification we can see rows on standard cells. They are placed as usual – back-2-back [PFET NFET] [NFET PFET] and hence reuse vertical lines of VCC и GND (surely power is fed from top metal all across it). You can tell PFET transistors as they are wider. Standard cell width is 1,83µm, which is consistent with 65nm manufacturing. On full resolution scale is 24.5nm per pixel.