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DarkRISCV – An Open Source RISC-V Core for FPGAs

RISC-V

DarkRISCV: An open source RISC-V implemented from scratch in one night! GitHub user darklife writes:

Developed in a magic night of 19 Aug, 2018 between 2am and 8am, the darkriscv is a very experimental implementation of the open source RISC-V instruction set. Nowadays, after one week of exciting sleepless nights of work (which explains the lots of typos you will found ahead), the darkriscv reached a very good quality result, in a way that the “hello world” compiled by the standard riscv-elf-gcc is working fine!

See the GitHub repository for the full story on implementing RISC-V for FPGAs and the code to do so.


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1 Comment

  1. Hey,
    check out my implementation of the RISC-V architecture. I worked on a fully compatible RV32I core since 2015 and it works (and can be easily ported to) on several FPGAs. Example software included, simulators, libraries and even a RTOS. A version of this core was fabricated and validated in silicon (TSMC 180nm). https://github.com/sjohann81/hf-risc

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