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Designing a RISC-V CPU in VHDL: deploy onto Digilent’s Arty S7 board

Designing a RISC-V CPU in VHDL, Part 16: Arty S7 RPU SoC, Block Rams, 720p HDMI

Domipheus Labs continues its series on designing a RISC-V CPU in VHDL for an FPGA.

I wanted to get an off-the-shelf Spartan 7 FPGA board, essentially to bring up the FPGA side of an eventual move to my own development board. When I saw the Digilent Arty S7 announced last year, I kept an eye on it knowing it would be a contender for my upgrade path to the 7-series chips. The Arty S7 I ended up purchasing is the S7-50 variant, sporting the XC7S50 Spartan 7 FPGA with significantly more resources than my previous Spartan 6 board. It also had 256MB DDR3 RAM, but lacked HDMI connectivity. Thankfully, the HDMI/DVI-D output issue has been solved.

You can read all the details on the blog post.


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