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An open Verilog implementation of the DisplayPort protocol for FPGAs #FPGA #DisplayPort #Verilog

 ᴊᴀᴄʜʏᴍ ᴍɪᴄʜᴀʟ @jachymmichal

Michael Field writes on Twitter:

I’ve uploaded my IP-free Verilog FPGA DisplayPort Implementation to a new Github repo. Feel free to take a look around, and try it on your board. My Verilog skills are weak, so any help would be greatly received.

The corresponding GitHub repo states:

DisplayPort_Verilog

A open Verilog implementation of DisplayPort protocol for FPGAs

DisplayPort is quite a complex protocol. This is a minimal Verilog implementation in the Verilog Language. Hopefully this will inspire others to improve on this.

This early version support a single lane (2.7Gb/s) and displays a white 800×600 screen, can scale to support four lanes and 4k resolutions.

My own test board is a Digilent Inc Nexys Video, using an Xilinx Artix 7 FPGA. However the most of the hardware specific parts are limited to the transceivers which can be replaced to support FPGAs from other vendors.


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