The Genius of RISC-V Microprocessors #RISCV

Erik Engheim posts on Medium on how the instruction set for RISC-V processors has been designed, cleverly for both simplicity and high performance.

… Some of the things which really impress me about the RISC-V ISA:

  1. It is a RISC instruction set which is small and easy to learn (47 in base). Very favorable to anyone interested in learning about microprocessors. RISC-V Cheat Sheet.
  2. Dominant architecture used for teaching digital design in universities: Why Universities Want RISC-V.
  3. It is cleverly designed to allow CPU builders to create high performance microprocessors using a RISC-V ISA.
  4. With no license fees and being designed to allow simple hardware implementations, a dedicated hobbyist could in principle make his own RISC-V CPU design in reasonable time.
  5. Open Source designs readily available to modify and play with: The Berkeley Out-of-Order (BOOM) RISC-V Processor.

Read more on Medium


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