NEORV32: a customizable RISC-V SoC #RISCV #FPGA

The NEORV32 Processor is a customizable microcontroller-like system on chip (SoC) that is based on the RISC-V NEORV32 CPU. The project is intended as auxiliary processor in larger SoC designs or as ready-to-go stand-alone custom / customizable microcontroller.

When I started to dive into the emerging RISC-V ecosystem I felt overwhelmed by the complexity. As a beginner it is hard to get an overview – especially when you want to setup a minimal platform to tinker with: Which core to use? How to get the right toolchain? What features do I need? How does the booting work? How do I create an actual executable? How to get that into the hardware? How to customize things? Where to start???

So this project aims to provides a simple to understand and easy to use yet powerful and flexible platform that targets FPGA and RISC-V beginners as well as advanced users.

The NEORV32 is not based on another RISC-V core. It was build entirely from ground up (just following the official ISA specs) having a different design goal in mind. The project does not intend to replace certain RISC-V cores or just beat existing ones like VexRISC in terms of performance or SERV in terms of size.

The project aims to provide another option in the RISC-V / soft-core design space with a different performance vs. size trade-off and a different focus: embrace concepts like documentation, platform-independence / portability, RISC-V compatibility, customization and ease of use.

Read more in the project GitHub repo here.


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