The first RISC-V computer chip lands at the European Processor Initiative #RISCV #EU
The European Processor Initiative (EPI) has run the successful first test of its RISC-V-based European Processor Accelerator (EPAC), touting it as the initial step towards homegrown supercomputing hardware, reports The Register.
EPI, launched back in 2018, aims to increase the independence of Europe’s supercomputing industry from foreign technology companies. At its heart is the adoption of the free and open-source RISC-V instruction set architecture for the development and production of high-performance chips within Europe’s borders.
The project’s latest milestone is the delivery of 143 samples of EPAC chips, accelerators designed for high-performance computing applications and built around the free and open-source RISC-V instruction set architecture. Designed to prove the processor’s design, the 22nm test chips – fabbed at GlobalFoundries, the not-terribly-European semiconductor manufacturer spun out of AMD back in 2009 – have passed initial testing, running a bare-metal “hello, world” program as proof of life.
The EPAC 1.0 chip is an undeniable team effort: it includes “micro-tile” vector processing cores designed by SemiDynamics, a dedicated vector processing unit from the Barcelona Supercomputing Centre and the University of Zagreb, a “home node” designed by Chalmers, L2 cache from FORTH, a Stencil and Tensor Accelerator (STX) from Fraunhofer, ITWM, and ETH Zürich, and a variable-precision processor – designed to accelerate deep learning workloads – created by CEA LIST, all tied together with a network-on-chip and high-speed serial system created by EXTOLL.
The EPI project has confirmed it is working to validate the other IP blocks on the chip, which targets a 1GHz operating frequency in its current FCBGA-packaged test-chip incarnation.
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