Addressing Criticism of RISC-V Microprocessors #RISCV @erikengheim @Medium

Erik Engheim cuts through the misconceptions of RISC-V when compared to ARM processor architectures. There seem to be a bit of rivalry between the ARM and RISC-V camps developing. It is perhaps not without reason. RISC-V and ARM represent quite radically different philosophies about how a RISC chip should be designed.

Eight myths of RISC-V are explored:

  • Myth 1: RISC-V Instruction-Set Bloats Programs
  • Myth 2: Variable Length Instructions Complicate Parallel Instruction Decoding
  • Myth 3: Not Having Conditional Execution Was a Mistake
  • Myth 4: RISC-V uses old outdated vector processing instead of modern SIMD instructions
  • Myth 5: Don’t Need Vector processing, Just Use Graphics Cards
  • Myth 6: A Modern ISA Must Handle Integer Overflow
  • Myth 7: Integer Overflow Handling is Bloated
  • Myth 8: Integer Overflow is Cheap To Implement

Read more in the in-depth article in Medium.

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