Making a MIPI CSI 2 Camera Receiver #SBC #Standards #Video #FPGA
If you’ve ever worked with a Raspberry Pi, you’ve probably heard of the Raspberry Pi Camera Module. But what is the ribbon cable that comes out of it? The modules use interfaces created by the MIPI Alliance: Camera Serial Interface v2 and Camera Control Interface.
CSI uses low voltage differential signaling (LVDS) to transmit packets of data from the camera module to the receiver. There are a total of up to 5 LVDS pairs. The first is the clock. The clock frequency is configured via MIPI CCS. The four remaining pairs, referred to as lanes, transmit the data itself. More lanes means a higher possible framerate and larger resolutions since bandwidth can be doubled, tripled or even quadrupled. There are two types of packets: short and long. Long packets contain image data as a line of pixels in the image, or some other embedded data. Short packets usually contain control information (i.e. start/end of line, start/end of frame, etc.).
Technically, CSI is implemented on top of MIPI D-PHY, which defines the low-level physical and electrical characteristics of the interface. There should be a secondary low-power function on each lane including the clock that detects when a packet will begin and end.
The image above shows a block diagram of MIPI (from here). On one side there is application processor and other side is the peripheral. When peripheral is a camera, CSI applies (DSI for displays).
Though MIPI is closed specification, which means one has to be member of MIPI consortium to gain access to full specification. And membership of the consortium comes with a big price tag for individuals. Luckily, full specifications are already available just a right keyword web search away. DCS, CCS, DSI, CSI and DPHY are all specified and available with just few minutes of web search.
Interfaces are often made with FPGAs. There is a GitHub site which describes making a MIPI CSI 2 Receiver for Raspberry Pi. See the Blog Post here.
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