A system for debugging logic chips in-circuit automatically
Evan’s Techie-Blog writes about using an FPGA shield (giving 64 bits of bidirectional 5v tolerant IO to a Spartan 6) for debugging logic chips.
This project is intended to allow for the in-circuit testing of 74xx and 40xx style logic chips. We do that by sampling all the pins of a given chip (inputs and outputs) and compare the behavior of the real chip to one that we model in verilog. This lets the circuit operate normally, wiggling the input pins and we can track those changes and compare them to the chip’s output pins. From this we can get an idea of whether a chip is bad, but the chip under test is not necessarily causing the issue, it’s possible that something on the same net as the output pin is interfering with the signal.
The first thing we do is take the pins that we’re measuring going into our real 74s04 and run them into our model of a 7404, the output data from that model then gets run into the comparator as well as our sampling clock and the actual pins coming from our measured chip. The output from this model is a signal that represents a discrepancy between the model and the actual chip.
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