Adventures in PC Emulation dives deep into the bus logic of the 8088 microprocessor, looking at the instruction pipeline.

A single bus cycle on the 8088 takes a minimum of 4 CPU cycles, consisting of 4 T-states numbered T1, T2, T3 and T4.

Ken Shirriff, in his analysis of the 8086’s silicon, was the first to document this, to my knowledge, on his blog entry, Reverse-engineering the 8086 processor’s address and data pin circuits.

He states,

There [are] two undocumented T states that are important to the bus cycle. The physical address is computed in the two clock cycles before T1 so the address will be available in T1. I give these “invisible” T states the names TS (start) and T0.

I originally missed the significance of this – it’s casually mentioned as if it were an interesting, but ultimately trivial internal detail. However these cycles are fundamental to the timing and operation of the 8088. They are not quite “invisible” after all!

Take a look at the detailed analysis in the post here.