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“RISC architecture is gonna change everything” …. Adafruit joins the RISC-V Foundation @risc_v #RISCV @adafruit #adafruit
— by phillip torrone
Filed under: announce, breaking news, featured, RISC-V — 

Alibaba’s chip division releases first core processor IP (based on RISC-V) @AlibabaGroup #riscv
— by phillip torrone
Filed under: maker business, RISC-V — 
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SiFive is a startup to pay attention to. RISC-V is here to stay. #makerbusiness
— by Teddy Papes
Filed under: maker business, manufacturing, RISC-V — 
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Building a RISC-V PC – now a reality @risc_v @ABOpenLtd @Hackaday
— by Mike Barela
Filed under: computers, fpga, microprocessors, RISC-V — 
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The SweRV RISC-V Core from Western Digital #RISCV #opensource #risc_v @westerndigital @WesternDigiCTO
— by Mike Barela
Filed under: internet of things, open source, RISC-V — 
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First four core RISC-V based FPGA SoC runs Linux #RiscV #FPGA #Linux @MicrochipTech
— by Mike Barela
Filed under: fpga, microprocessors, RISC-V — 
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Feather-compatible FPGAs @TmmMcci @MCCI #LoRaWAN #IoT @TinyFPGA⁩ ⁦@latticesemi⁩ ⁦@risc_v
— by phillip torrone
Filed under: feather, fpga, RISC-V — 
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RISC OS is open for business! #OpenSource
— by Mike Barela
Filed under: open source, RISC-V, software — 
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Designing a RISC-V CPU in VHDL: deploy onto Digilent’s Arty S7 board
— by Mike Barela
Filed under: fpga, RISC-V — 
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Prisca Dorcas Mojica Rodriguez #HispanicHeritageMonth
— by Takara
Filed under: holiday, RISC-V — 
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DarkRISCV – An Open Source RISC-V Core for FPGAs
— by Mike Barela
Filed under: fpga, RISC-V — 
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RISC-V Keynote at Embedded Linux Conference 2018 @linuxfoundation @SiFiveInc
— by phillip torrone
Filed under: open source hardware, RISC-V — 
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UT Austin’s Briscoe Center for American History Acquires Stephen Shames’ Photo Archive #ArtTuesday
— by Stephanie
Filed under: art, history, photography, RISC-V — 
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Inventors of RISC Processors Win $1 Million Turing Prize
— by chris y
Filed under: arm development, breaking news, RISC-V — 
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LoFive RISC-V @groupgetscom @SiFiveInc
— by phillip torrone
Filed under: Breakout Boards, RISC-V — 
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